Semiconductor device

ABSTRACT

An active barrier structure has a p-type region and an n-type region, each of which is in contact with a p-type impurity region and which are ohmic-connected to each other to attain a floating potential. A trench isolation structure is formed between an active barrier region and the other region (an output transistor formation region and a control circuit formation region). The trench isolation structure has a trench extending from the main surface of the semiconductor substrate through then epitaxial layer to reach the p-type impurity region. Therefore, a semiconductor device is obtained which allows the chip size to be reduced easily and is highly effective in preventing movement of electrons from the output transistor formation region to the other element formation region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and moreparticularly to a semiconductor device having an output elementformation region, an other element formation region, and an activebarrier region arranged between the output element formation region andthe other element formation region.

2. Description of the Background Art

In products used for automobiles, motor drive, audio amplifiers, and thelike, an L (self inductance) load sometimes producescounter-electromotive force to cause the drain (n-type region) of anoutput transistor to have a negative potential. In this case, thenegative potential allows electrons to be injected from the drain to ap-type substrate and move from an output transistor formation region toan other element formation region through the p-type substrate, causingthe other elements to malfunction. To solve this problem, an activebarrier region may be formed between the output transistor formationregion and the other element formation region.

This active barrier region is formed such that a p-type region and ann-type region having a floating potential are ohmic-connected through aconductive layer, as disclosed in the following document: A. R. Stella,et al., “Novel achievements in the understanding and suppression ofparasitic minority carrier currents in P⁻ epitaxy/P⁺⁺ Substrate SmartPower Technologies,” Proceedings of 2004 International Symposium onPower Semiconductor Devices & ICs, Kitakyushu, pp. 423-426.

More specifically, electrons injected into a p-type substrate disappearin the p-type substrate due to recombination or are taken into then-type region of the active barrier region. Since electrons are takeninto the n-type region of the active barrier region, the n-type regionattains a positive potential. When the n-type region attains a positivepotential, the p-type region of the active barrier region attains anegative potential in order to cancel this, because the p-type regionand the n-type region having a floating potential are ohmic-connectedthrough the conductive layer in the active barrier region. When thep-type region of the active barrier region attains a negative potential,the electrons injected into the p-type substrate hardly move forwardfrom the p-type region having a negative potential. Therefore, electronshardly reach the other element formation region from the active barrierregion, preventing a malfunction of the other elements.

However, in conventional semiconductor devices, the active barrierregion and the output transistor formation region as well as the activebarrier region and the other element formation region are electricallyisolated from each other by a pn junction. In the isolation structureusing this pn junction, impurity diffusion in the impurity diffusionregion forming the isolation structure inevitably increases the size ofthe isolation structure, so that the chip size cannot be decreased.

In addition, in the isolation structure using a pn junction, the effectof preventing the movement of electrons from the output transistorformation region to the other element formation region is not enough.

SUMMARY OF THE INVENTION

The present invention is made in view of the aforementioned problem, andthe object of the present invention is to provide a semiconductor devicewhich allows the chip size to be reduced easily and is highly effectivein preventing movement of electrons from an output transistor formationregion to an other element formation region.

A semiconductor device in the present embodiment has an output elementformation region, an other element formation region, and an activebarrier region arranged between the output element formation region andthe other element formation region. The semiconductor device includes asemiconductor substrate, a first region of a first conductivity type, asecond region of a second conductivity type, an active barrierstructure, and a trench isolation structure. The semiconductor substratehas a main surface. The first region of the first conductivity type isformed in the semiconductor substrate in the output element formationregion, the other element formation region, and the active barrierregion. The second region of the second conductivity type is formed inthe semiconductor substrate in the output element formation region, theother element formation region, and the active barrier region so as toform a pn junction with the first region and to be positioned on themain surface side of the semiconductor substrate rather than the firstregion. The active barrier structure has a third region of the firstconductivity type and a fourth region of the second conductivity type,each of which is in contact with the first region and which areohmic-connected to each other to attain a floating potential, in theactive barrier region. The trench isolation structure has a trenchformed at least either between the active barrier region and the outputelement formation region or between the active barrier region and theother element formation region and formed to extend from the mainsurface of the semiconductor substrate through the second region andthen reach the first region.

In accordance with the semiconductor device in the present embodiment, atrench isolation structure is formed at least either between the activebarrier region and the output element formation region or between theactive barrier region and the other element formation region. Because ofisolation by a trench in this manner, the two-dimensional area occupiedby the isolation structure can be made smaller than the isolation usinga pn junction. Therefore, the chip size can easily be reduced.Furthermore, the trench is formed to extend from the main surface of thesemiconductor substrate through the second region to reach the firstregion. Thus, carriers based on counter-electromotive force injectedfrom the output element cannot reach the other element formation regionwithout bypassing the trench. Accordingly, the movement path of carriersfrom the output element formation region to the other element formationregion becomes longer, thereby increasing the possibility that thecarriers disappear in the course due to recombination. Therefore, themovement of carriers based on counter-electromotive force from theoutput element formation region to the other element formation regioncan be inhibited, thereby preventing a malfunction of the otherelements.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing that an output element is connectedto an inductive load in a semiconductor device in a first embodiment ofthe present invention.

FIG. 2 is a plan view schematically showing a configuration of thesemiconductor device in the first embodiment of the present inventionhaving the output element shown in FIG. 1.

FIG. 3 is a schematic plan view showing an enlarged view of a region Rin FIG. 2.

FIG. 4 is a schematic cross-sectional view taken along line IV-IV inFIG. 3.

FIG. 5 to FIG. 7 are schematic cross-sectional views showing the stepsof a method of manufacturing the semiconductor device in the firstembodiment of the present invention, in order.

FIG. 8 is a cross-sectional view schematically showing a configurationin which an active barrier region and an output transistor formationregion are isolated from each other by a p-type diffusion region.

FIG. 9 is a schematic cross-sectional view showing electrons injectedfrom a MOS transistor of an output element in the structure shown inFIG. 8.

FIG. 10 is a diagram showing the proportion of electrons reaching ann-type diffusion region (n epitaxial layer EP) on the electron receivingside (the control circuit formation region CCR side) depending on thepresence or absence of the active barrier region.

FIG. 11 is a diagram showing how the current ratio (Iepi/Iin) changeswith respect to current Iin on the electron injection side for thestructure in FIG. 4 and the structure in FIG. 8.

FIG. 12 is a cross-sectional view schematically showing a configurationin which an n-type diffusion region NR4 is added to the active barrierstructure in FIG. 4.

FIG. 13 is a view for illustrating a method of manufacturing theconfiguration in FIG. 12.

FIG. 14 is a cross-sectional view schematically showing a configurationof a semiconductor device in a second embodiment of the presentinvention.

FIG. 15 is a diagram showing the changing current ratio (|Iepi/Iin|)with respect to the distance between n-type diffusion regions for thestructure shown in FIG. 14 and the structure shown in FIG. 4.

FIG. 16 is a cross-sectional view schematically showing a configurationin which n-type diffusion region NR4 is added to the active barrierstructure in FIG. 14.

FIG. 17 is a cross-sectional view schematically showing a configurationof a semiconductor device in a third embodiment of the presentinvention.

FIG. 18 is a diagram showing the changing current ratio (|Iepi/Iin|)with respect to the distance between n-type diffusion regions for thestructure shown in FIG. 17 and the structure shown in FIG. 8.

FIG. 19 is a cross-sectional view schematically showing a configurationin which n-type diffusion region NR4 is added to the active barrierstructure in FIG. 17.

FIG. 20 is a cross-sectional view schematically showing a configurationin which an IGBT is employed as an output element.

FIG. 21 is a cross-sectional view schematically showing a configurationin which a diode is employed as an output element.

FIG. 22 is a schematic cross-sectional view showing that a plurality ofactive barrier structures are formed between an output transistorformation region OER and a control circuit formation region CCR.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, the embodiments of the present invention will bedescribed based on the figures.

First Embodiment

Referring to FIG. 1, an output element formed in a semiconductor chipincludes, for example, a high-voltage High side n-channel MOS (MetalOxide Semiconductor) transistor (referred to as an nMOS transistorhereinafter) HTR and a high-voltage Low side nMOS transistor LTR.

A diode D1 is formed between the back gate and the drain of each of nMOStransistor HTR and nMOS transistor LTR. In addition, a diode D2 isformed between a p-type semiconductor substrate and the drain of each ofnMOS transistor HTR and nMOS transistor LTR.

The source of nMOS transistor HTR and the drain of nMOS transistor LTRare electrically connected to each other and are electrically connectedto an inductive load (for example, a coil) IL arranged on the outside ofthe semiconductor chip.

It is noted that an output element refers to an element electricallyconnected to an electronic device arranged on the outside of asemiconductor chip.

Referring to FIG. 2, a semiconductor chip CP has, for example, arectangular shape as two-dimensionally viewed. This semiconductor chipCP has a plurality of output transistor formation regions OER, a controlcircuit formation region CCR, and a plurality of active barrier regionsABR.

Output transistor formation region OER has an output element shown inFIG. 1. Control circuit formation region CCR has other elements forcontrolling the output element formed in output transistor formationregion OER.

Active barrier region ABR is formed between output transistor formationregion OER and control circuit formation region CCR and between outputtransistor formation region OER and output transistor formation regionOER.

Furthermore, active barrier region ABR may be formed in control circuitformation region CCR so as to surround the periphery of a particularcircuit CC in control circuit formation region CCR. This particularcircuit CC surrounded by active barrier region ABR is, for example, ananalog detection circuit (comparator, detector circuit), asample-and-hold circuit, a voltage/current control circuit for an outputtransistor, a bandgap circuit, a DC-DC converter circuit, an oscillator,a phase locked loop (PLL) circuit, a charge pump circuit, or the like.

Referring to FIG. 3 and FIG. 4, a semiconductor substrate SUB is formedof for example, a p-type silicon substrate. In output transistorformation region OER, control circuit formation region CCR, and activebarrier region ABR, a p-type impurity region (first region) PSR isformed in semiconductor substrate SUB.

An n-type epitaxial layer (second region) EP is formed so as to form apn junction with p-type impurity region PSR and to be located on themain surface side of semiconductor substrate SUB rather than p-typeimpurity region PSR. This n-type epitaxial layer EP is formed insemiconductor substrate SUB, in output transistor formation region OER,control circuit formation region CCR, and active barrier region ABR.N-type epitaxial layer EP has a concentration of, for example, 2.6×10¹⁵cm⁻³ to 3.4×10¹³ cm⁻³.

A field insulating layer FI formed of, for example, a LOCOS (LocalOxidation of Silicon) oxide film is selectively formed on the mainsurface of semiconductor substrate SUB.

In output transistor formation region OER, a buried n⁺ diffusion regionNE is formed between p-type impurity region PSR and n-type epitaxiallayer EP. In addition, in output transistor formation region OER, forexample, high-voltage nMOS transistors HTR, LTR shown in FIG. 1 and thelike are formed as output elements on the main surface of semiconductorsubstrate SUB.

This high-voltage nMOS transistor mainly has an n⁺ drain region DR, ann⁻ epitaxial layer EP, a p-type back gate region BR, an n⁺ source regionSR, a gate insulating layer GI, and a gate electrode layer GE.

N⁺ drain region DR is formed on the main surface of semiconductorsubstrate SUB in n⁻ epitaxial layer EP. P-type back gate region BR isformed on the main surface of semiconductor substrate SUB in n⁻epitaxial layer EP, and field insulating layer FI is sandwiched betweenp-type back gate region BR and n⁺ drain region DR. N⁺ source region SRis formed on the main surface of semiconductor substrate SUB withinp-type back gage region BR. Gate electrode layer GE is formed on p-typeback gate region BR sandwiched between n⁺ source region SR and n⁻epitaxial layer EP with gate insulating layer GI interposed therebetweenand partially lies on field insulating layer FI.

In output transistor formation region OER, an interlayer insulatinglayer II is formed to cover the high-voltage nMOS transistor. In thisinterlayer insulating layer II, a contact hole CH is formed whichreaches each of n⁺ drain region DR and n⁺ source region SR, and a plugconductive layer PL is formed in each of these contact holes CH. Aninterconnection layer CL is formed on interlayer insulating layer II toelectrically connect to each of n⁺ drain region DR and n⁺ source regionSR through plug conductive layer PL.

In control circuit formation region CCR, a buried n⁺ diffusion region NEis formed between p-type impurity region PSR and n-type epitaxial layerEP. In addition, in control circuit formation region CCR, a variety ofelements for controlling an output element and the like are formed onthe main surface of semiconductor substrate SUB.

Furthermore, in control circuit formation region CCR, the aforementionedinterlayer insulating layer II is formed to cover a variety of elementsfor controlling an output element and the like. In this interlayerinsulating layer II, contact hole CH is formed which reaches an n⁺diffusion region NR3, and plug conductive layer PL is formed in contacthole CH. Interconnection layer CL is formed on interlayer insulatinglayer II to electrically connect to n⁺ diffusion region NR3 though plugconductive layer PL.

In active barrier region ABR, an active barrier structure is formed.This active barrier structure has a p-type region (third region) and ann-type region (fourth region), each of which is in contact with p-typeimpurity region PSR and which are ohmic-connected to each other througha conductive layer to attain a floating potential. The p-type regionthat forms the active barrier structure has a buried p-type diffusionregion PE, a p-type diffusion region PR2, and a p⁺ diffusion region PR3.Buried p-type diffusion region PE is formed on p-type impurity regionPSR in contact therewith. This buried p-type diffusion region PE has aconcentration of, for example, 1.0×10¹⁶ cm⁻³ to 6.0×10¹⁶ cm⁻³. P-typediffusion region PR2 is formed on buried p-type diffusion region PE incontact therewith. P⁺ type diffusion region PR3 is formed on the mainsurface of semiconductor substrate SUB within p-type diffusion regionPR2.

On the other hand, the n-type region that forms the active barrierstructure has a buried n⁺ diffusion region NE, n⁻ epitaxial layer EP,and an n⁺ diffusion region NR1. Buried n⁺ diffusion region NE is formedbetween p-type impurity region PSR and n⁻ epitaxial layer EP. N⁺diffusion region NR1 is formed on the main surface of semiconductorsubstrate SUB in n⁻ epitaxial layer EP.

The conductive layer that ohmic-connects the p-type region and then-type region forming the active barrier structure has a pair of plugconductive layers PL and a conductive layer FCL. Each of a pair of plugconductive layers PL is formed in contact hole CH formed in theaforementioned interlayer insulating layer II. One of a pair of plugconductive layers PL is ohmic-connected to p⁺ diffusion region PR3 andthe other of a pair of plug conductive layers PL is ohmic-connected ton⁺ diffusion region NR1. Conductive layer FCL is formed on interlayerinsulating layer II and is electrically connected to each of a pair ofplug conductive layers PL as described above.

In the present embodiment, a trench isolation structure TI is formed atleast either between active barrier region ABR and output transistorformation region OER or between active barrier region ABR and controlcircuit formation region CCR. This trench isolation structure TI has atrench TR, a buried insulating layer EI, and a p⁺ diffusion region(fifth region) PR1.

Trench TR is formed to extend from the upper surface of field insulatinglayer FI formed on the main surface of semiconductor substrate SUBthrough field insulating layer FT and n⁻ epitaxial layer EP and thenreach p-type impurity region PSR.

Preferably, this trench TR extends to a position deeper than thelowermost part of each of buried p-type diffusion region PE and buriedn⁺ diffusion region NE relative to the main surface of semiconductorsubstrate SUB. Buried insulating layer EI is buried in trench TR. P⁺diffusion region PR1 is formed in p-type impurity region PSR to surroundthe lower end part of trench TR.

Now, a method of manufacturing a semiconductor device in accordance withthe present embodiment will be described.

Referring to FIG. 5, the surface of semiconductor substrate SUB formedof p-type impurity region PSR is oxidized so that a silicon oxide film(not shown) having a thickness of, for example, 300 nm to 1000 nm isformed on that surface. By the usual photolithography technique, aphotoresist pattern (not shown) is formed on the silicon oxide film.Using this resist pattern as a mask, the silicon oxide film is etchedand then patterned. Thereafter, the resist pattern is removed, forexample, by ashing or the like.

Using the patterned silicon oxide film as a mask, the main surface ofp-type semiconductor substrate SUB is subjected to ion implantation of,for example, antimony. Thereafter, heat treatment is performed at, forexample, 1240° C. so that n⁺ diffusion region NE is formed on the mainsurface of semiconductor substrate SUB. Thereafter, the silicon oxidefilm on the main surface of semiconductor substrate SUB is removed.

The surface of p-type semiconductor substrate SUB is oxidized so that asilicon oxide film (not shown) having a thickness of, for example, 20 nmto 30 nm is formed on that surface. By the usual photolithographytechnique, a photoresist pattern (not shown) is formed on the siliconoxide film. Using this resist pattern as a mask, the silicon oxide filmis etched and then patterned.

Using the patterned silicon oxide film as a mask, the main surface ofp-type semiconductor substrate SUB is subjected to ion implantation of,for example, boron. Thereafter, the resist pattern is removed, forexample, by ashing or the like. Then, p-type diffusion region PE isformed on the main surface of semiconductor substrate SUB by performingannealing at a temperature of for example, 1150° C. Thereafter, thesilicon oxide film on the main surface of semiconductor substrate SUB isremoved.

Then, the main surface of semiconductor substrate SUB having n⁺diffusion region NE and p-type diffusion region PE formed thereinundergoes epitaxial growth so that an n⁻ epitaxial layer EP is formed onthe main surface of semiconductor substrate SUB.

Referring to FIG. 6, the surface of n⁻ epitaxial layer EP (the mainsurface of semiconductor substrate SUB) is oxidized so that a siliconoxide film (not shown) having a thickness of for example, 20 nm to 30 nmis formed on that surface. By the usual photolithography technique, aphotoresist pattern (not shown) is formed on that silicon oxide film.Using this resist pattern as a mask, the silicon oxide film is etchedand then patterned. Thereafter, the resist pattern is removed, forexample, by ashing or the like.

Using the patterned silicon oxide film as a mask, the surface of n⁻epitaxial layer EP is subjected to ion implantation of, for example,boron so that a p-type diffusion region PR2 is formed. Thereafter, theresist pattern is removed, for example, by ashing or the like. Then,field insulating layer FI is selectively formed on the main surface ofsemiconductor substrate SUB by LOCOS method.

Referring to FIG. 7, after oxidation of 300 nm to 1000 nm is performed,a resist pattern is formed by a photolithography technique, and usingthe resist pattern as a mask, field insulating layer FI is selectivelyetched away. Thereafter, the resist pattern is removed, for example, byashing or the like.

Then, using field insulating layer FI as selectively etched away as amask, semiconductor substrate SUB is etched so that trench TR is formedin semiconductor substrate SUB. Oxidation is performed so that a siliconoxide film having a thickness of, for example, 20 nm to 30 nm is formedon the wall surface of trench TR. Thereafter, through ion implantationof boron, p⁺ diffusion region PR1 is formed in semiconductor substrateSUB to surround the lower end part of trench TR. Thereafter, a siliconoxide film is deposited so that buried insulating layer EI is formed tofill in trench TR.

Referring to FIG. 4, the silicon oxide film is etched by a few tens ofnm so that the main surface of semiconductor substrate SUB is exposed inthe region where field insulating layer FI is not formed. Thereafter,through thermal oxidation, gate insulating layer GI formed of a siliconoxide film having a thickness of, for example, a few tens of nm isformed on the main surface of the exposed semiconductor substrate SUB.

Thereafter, an impurity-doped polysilicon film (referred to as a dopedpolysilicon film hereinafter) and a tungsten silicide (WSi₂) layer arelaid on the entire surface in order. By the usual photolithographytechnique and etching technique, the laid doped polysilicon film andtungsten silicide layer are patterned, resulting in gate electrode layerGE.

Then, a resist pattern is formed by a photolithography technique, andusing the resist pattern, the gate electrode, and the like as a mask,the main surface of semiconductor substrate SUB is subjected to ionimplantation of for example, boron. Therefore, p-type back gate regionBR is formed on the main surface of semiconductor substrate SUB.Thereafter, the resist pattern is removed.

Then, a resist pattern is formed by a photolithography technique, andthen using the resist pattern, the gate electrode and the like as amask, the main surface of semiconductor substrate SUB is subjected toion implantation of, for example, arsenic. Therefore, n⁺ diffusionregions DR, SR, NR1, NR3 are formed on the main surface of semiconductorsubstrate SUB. Thereafter, the resist pattern is removed.

Then, a resist pattern is formed by a photolithography technique, andusing the resist pattern, the gate electrode, and the like as a mask,the main surface of semiconductor substrate SUB is subjected to ionimplantation of, for example, boron. Therefore, p⁺ diffusion region PR3is formed on the main surface of semiconductor substrate SUB.Thereafter, the resist pattern is removed.

Then, interlayer insulating layer II formed of, for example, a siliconoxide film is formed at a thickness of 500 nm to 1000 nm. Thereafter, bythe usual photolithography technique and etching technique, contact holeCH which reaches each of n⁺ diffusion regions DR, SR, NR1, NR3 and p⁺diffusion region PR3 is formed in interlayer insulating layer II.

A stacked film of a titanium (Ti) layer and a titanium nitride (TiN)layer and a tungsten (W) film, for example, are formed so as to fill incontact hole CH and are thereafter left only in contact hole CH byperforming etching. Therefore, plug conductive layer PL is formed whichfills in contact hole CH.

Then, after a conductive layer formed of, for example, AlCu or AlSiCu isdeposited on interlayer insulating layer II, this conductive layer ispatterned by the usual photolithography technique and etching technique,resulting in interconnection layer CL and conductive layer FCL.

As described above, a semiconductor device in accordance with thepresent embodiment is thus fabricated.

Now, the operation and effect of the semiconductor device in accordancewith the present embodiment will be described.

Referring to FIG. 8, this structure differs from the configuration ofthe first embodiment shown in FIG. 4 in that the active barrier regionand the output transistor formation region are isolated from each otherby a p-type diffusion region.

The p-type diffusion region which isolates active barrier region ABRfrom output transistor formation region OER has buried p-type diffusionregion PE and p-type diffusion region PR2. Buried p-type diffusionregion PE of the p-type diffusion region for isolation is fabricated inthe same manufacturing step as buried p-type diffusion region PE thatforms the active barrier structure. Furthermore, p-type diffusion regionPR2 of the p-type diffusion region for isolation is fabricated in thesame manufacturing step as p-type diffusion region PR2 that forms theactive barrier structure.

Buried p-type diffusion region PE and p-type diffusion region PR2 thatform the active barrier structure also serve as a p-type diffusionregion which isolates active barrier region ABR from control circuitformation region CCR.

The other configuration of the structure in FIG. 8 is almost the same asthe configuration in the foregoing first embodiment, and therefore thesame components are denoted with the same characters and the descriptionthereof will not be repeated. When the output transistor in FIG. 8 isconnected to inductive load IL as shown in FIG. 1 and when MOStransistor HTR shown in FIG. 1 is in the ON state and MOS transistor LTRis in the OFF state, current flows from MOS transistor HTR intoinductive load IL. In this state, when MOS transistor LTR is switched tothe ON state with MOS transistor HTR in the OFF state, inductive load ILtends to keep current flowing. Thus, an electromotive force occurs, sothat current flows through parasitic diodes D1, D2 of MOS transistorLTR.

More specifically, in FIG. 8, n⁺ drain region DR of high-voltage nMOStransistor in the output transistor formation region attains a negativepotential, and as shown by the arrow in FIG. 9, electrons are injectedfrom n⁺ drain region DR into p-type impurity region PSR of semiconductorsubstrate SUB. The electrons injected into p-type impurity region PSRdisappear in p-type impurity region PSR due to recombination or aretaken into buried n⁺ diffusion region NE of active barrier region ABR.

Electrons are taken into buried n⁺ diffusion region NE of active barrierregion ABR so that buried n⁺ diffusion region NE attains a positivepotential. Since the n-type region and the p-type region having afloating potential are ohmic-connected through the conductive layer inthe active barrier region ABR, when the n-type region attains a positivepotential, in order to cancel this, the p-type region (buried p-typediffusion region PE and p-type diffusion region PR2) of active barrierregion ABR attains a negative potential.

When the p-type region of active barrier region ABR attains a negativepotential, the electrons injected in p-type impurity region PSR hardlymove forward from the p-type region (buried p-type diffusion region PEand p-type diffusion region PR2) having a negative potential, and it ismore likely that the electrons disappear due to recombination. Thus, theelectrons hardly reach control circuit formation region CCR from activebarrier region ABR, thereby preventing a malfunction of the otherelements in control circuit formation region CCR.

In this manner, when electrons are injected from n⁺ drain region DR ofhigh-voltage nMOS transistor in output transistor formation region OERinto semiconductor substrate SUB, active barrier region ABR has afunction of preventing the electrons from reaching control circuitformation region CCR.

The axis of abscissas in FIG. 10 shows the distance between the n-typediffusion region (n⁻ epitaxial layer EP) on the electron injection side(the output transistor formation region OER side) and the n-typediffusion region (n⁻ epitaxial layer EP) on the electron receiving side(the control circuit formation region CCR side). Furthermore, the axisof ordinates shows the ratio (|Iepi/Iin|) of current Iepi on theelectron receiving side to current Iin on the electron injection side.

The result in FIG. 10 also indicates that when the distance between then-type diffusion regions is the same, electrons are less likely to reachthe electron receiving side in the structure having the active barrierregion than in the structure having no active barrier region.

In the configuration shown in FIG. 8, however, since the isolationbetween active barrier region ABR and the other region is achieved bythe p-type diffusion region (buried p-type diffusion region PE andp-type diffusion region PR2), the diffusion of impurity in the p-typediffusion region inevitably increases the two-dimensional area occupiedby the isolation region.

In addition, it has been found that in the isolation structure using thep-type diffusion region, the effect of preventing the movement ofelectrons from output transistor formation region OER to control circuitformation region CCR is not enough.

As a result of elaborate study, the inventor has found that when theisolation between active barrier region ABR and the other region isachieved by trench isolation, the two-dimensional occupied area can bereduced and, in addition, the effect of preventing movement of electronsfrom output transistor formation region OER to control circuit formationregion CCR can be enhanced.

In this regard, the inventor examined how the current ratio (Iepi/Iin)changed with respect to current Iin on the electron injection side forthe structure of the present embodiment shown in FIG. 4 and thestructure shown in FIG. 8. The result is shown in FIG. 11. It is notedthat the result in FIG. 11 is obtained when the distance between then-type diffusion region (n⁻ epitaxial layer EP) on the electroninjection side (the output transistor formation region OER side) and then-type diffusion region (n⁻ epitaxial layer EP) on the electronreceiving side (the control circuit formation region CCR side) is 300μm.

The result in FIG. 11 indicates that when the same current Iin flows onthe electron injection side, the current ratio (|Iepi/Iin|) is smallerin the structure in FIG. 4 than in the structure in FIG. 8 and electronsare less likely to reach the electron receiving side. It can be assumedthat this effect can be obtained by the following mechanism.

In the isolation by the pn junction shown in FIG. 8, n⁻ epitaxial layerEP and p-type diffusion regions PE, PR2 for isolation are formed on thesame monocrystal substrate so that electrons easily pass through this pnjunction. Therefore, electrons easily pass through this pn junction andreach control circuit formation region CCR from output transistorformation region OER through active barrier region ABR. On the contrary,in the structure of the present embodiment in FIG. 4, because of theformation of trench isolation, the continuity of crystal between n⁻epitaxial layer EP in active barrier region ABR and n⁻ epitaxial layerEP in the other region is interrupted by trench TR. In addition, sinceburied insulating layer EI is filled in trench TR, a different materialexists between n⁻ epitaxial layer EP in active barrier region ABR and n⁻epitaxial layer EP in the other region.

Thus, in the structure of the present embodiment in FIG. 4, the passageof electrons in the trench isolation is more difficult than the passagethrough the pn junction portion, so that electrons cannot reach theregion on the other side of the trench without bypassing the trenchisolation. Therefore, it is assumed that the probability that electronsdisappear due to recombination is increased and the proportion ofelectrons arriving at the electron receiving side from theelectrons-injected side is decreased.

Furthermore, the result shown in FIG. 11 is obtained when thetwo-dimensional size is the same in the isolation by p-type regions PE,PR2 shown in FIG. 8 and in the isolation by trench TR shown in FIG. 4.Therefore, even if the two-dimensional size of the isolation by trenchTR shown in FIG. 4 is made smaller than the two-dimensional size of theisolation by p-type regions PE, PR2 shown in FIG. 8, the obtained effectis equivalent or more. Thus, in the configuration of the presentembodiment shown in FIG. 4, the isolation structure is easily reduced insize and the chip size is easily decreased.

Here, as shown in FIG. 12, the n-type region that forms the activebarrier structure may have an n-type diffusion region NR4 other thanburied n⁺ diffusion region NE, n⁻ epitaxial layer EP, and n⁺ diffusionregion NR1. This n-type diffusion region NR4 is formed on buried n⁺diffusion region N in contact therewith on buried n⁺ diffusion regionNE. Furthermore, n⁺ diffusion region NR1 is formed on the main surfaceof the semiconductor substrate within n-type diffusion region NR4.

The other configuration of the structure shown in FIG. 12 is almost thesame with the configuration shown in FIG. 4, and therefore the samecomponents are denoted with the same characters and the descriptionthereof will not be repeated.

In a method of manufacturing the structure in FIG. 12, first, theprocess step shown in FIG. 5 is performed. Thereafter, referring to FIG.13, the outermost surface of n⁻ epitaxial layer EP is oxidized so that asilicon oxide film of a thickness of, for example, 300 nm to 1000 nm isformed. This silicon oxide film is patterned by the usualphotolithography technique and etching technique. Phosphoslicate glassis deposited on the patterned silicon oxide film, followed by heattreatment at a temperature of 1100° C. Thus, phosphorous diffuses fromphosphosilicate glass onto the surface of n⁻ epitaxial layer EP exposedfrom the silicon oxide film serving as a mask, resulting in n-typediffusion region NR4. Thereafter, the silicon oxide film used as a maskis removed.

Here, the subsequent steps are almost the same with those of the methodof manufacturing the structure shown in FIG. 4 and therefore thedescription thereof will not be repeated.

Second Embodiment

Referring to FIG. 14, the configuration of the present embodimentdiffers from the configuration of the first embodiment shown in FIG. 4in that a trench structure is added.

In the present embodiment, trench TR is formed to extend from the mainsurface of semiconductor substrate SUB to between buried p-typediffusion region PE and buried n⁺ diffusion region NE in active barrierregion ABR. Buried insulating layer EI is formed in trench TR. Inaddition, p⁺ diffusion region PR1 is formed to surround the lower endpart of trench TR.

This trench TR passes through n⁻ epitaxial layer EP to reach p-typeimpurity region PSR. Furthermore, this trench TR preferably extends to aposition deeper than the lowermost part of buried p-type diffusionregion PE and buried n⁺ diffusion region NE relative to the main surfaceof semiconductor substrate SUB.

Here, the other configuration of the structure of the present embodimentis almost the same with the configuration of the foregoing firstembodiment, and therefore the same components are denoted with the samecharacters and the description thereof will not be repeated.

Referring to FIG. 15, it is understood that by adding trench isolationas shown in FIG. 14, the proportion of electrons arriving at theelectron receiving side from the electron injection side can be furtherreduced.

As described above, in the present embodiment, the chip size can easilybe reduced, and in addition, the proportion of electrons arriving at theelectron receiving side from the electron injection side can be furtherreduced, thereby further preventing a malfunction of an element on theelectron receiving side.

Here, as shown in FIG. 16, the n-type region that forms the activebarrier structure may have n-type diffusion region NR4 other than buriedn⁺ diffusion region NE, n⁻ epitaxial layer EP, and n⁺ diffusion regionNR1. This n-type diffusion region NR4 is formed on buried n⁺ diffusionregion N in contact therewith on buried n⁺ diffusion region NE.Furthermore, n⁺ diffusion region NR1 is formed on the main surface ofthe semiconductor substrate within n-type diffusion region NR4.

Third Embodiment

Referring to FIG. 17, the configuration of the present embodimentdiffers from the configuration of the first embodiment shown in FIG. 4in that the p-type diffusion region and the n-type diffusion region thatform the active barrier structure are reversely arranged.

In the present embodiment, the p-type diffusion region (buried p-typediffusion region PE, p-type diffusion region PR2, p⁺ diffusion regionPR3) that forms the active barrier structure is positioned on the outputtransistor formation region OER side while the n-type diffusion region(buried n⁺ diffusion region NE, n⁺ diffusion region NR1) is positionedon the control circuit formation region CCR side.

Here, the other configuration of the structure of the present embodimentis almost the same with the configuration of the foregoing firstembodiment, and therefore the same components are denoted with the samecharacters and the description thereof will not be repeated.

Referring to FIG. 18, even when the p-type diffusion region and then-type diffusion region that form the active barrier structure arereversely arranged as shown in FIG. 17, the proportion of electronsarriving at the electron receiving side from the electron injection sideis reduced as compared with the configuration of FIG. 8.

As described above, in the present embodiment, the chip size can easilybe reduced and, in addition, the proportion of electrons arriving at theelectron receiving side from the electron injection side can be reduced,thereby preventing a malfunction of an element on the electron receivingside.

Here, as shown in FIG. 19, the n-type region that forms the activebarrier structure may have n-type diffusion region NR4 other than buriedn⁺ diffusion region NE, n⁻ epitaxial layer EP, and n⁺ diffusion regionNR1. This n-type diffusion region NR4 is formed on n⁺ diffusion region Nin contact therewith on buried n+ diffusion region NE.

Furthermore, n⁺ diffusion region NR1 is formed on the main surface ofthe semiconductor substrate within n-type diffusion region NR4.

Although in the first to third embodiments as described above, ahigh-voltage MOS transistor has been described as an output elementformed in output transistor formation region OER, an output element isnot limited thereto and may be an IGBT (Insulate Gate BipolarTransistor), a diode, or the like.

Referring to FIG. 20, an IGBT is formed as an output element in outputtransistor formation region OER. This IGBT has a p⁺ collector region CR,an n⁻ epitaxial layer EP, a p-type back gate region BR, an n⁺ sourceregion (emitter region) SR, and a gate insulating layer GI, and a gateelectrode layer GE.

P⁺ collector region CR is formed on the main surface of semiconductorsubstrate SUB within n⁻ epitaxial layer EP. P-type back gate region BRis formed on the main surface of semiconductor substrate SUB within n⁻epitaxial layer EP and is formed with field insulating layer FIinterposed between p-type back gate region BR and p⁺ collector regionCR. N⁺ source region SR is formed on the main surface of semiconductorsubstrate SUB within p-type back gate region BR. Gate electrode layer GEis formed on p-type back gate region BR sandwiched between n⁺ sourceregion SR and n⁻ epitaxial layer EP with gate insulating layer GIinterposed and partially lies on filed insulating layer FI.

Here, the other configuration in FIG. 20 is almost the same with theconfiguration of the first embodiment shown in FIG. 4 as describedabove, and therefore the same components are denoted with the samereference characters and the description thereof will not be repeated.

Referring to FIG. 21, a diode is formed as an output element in outputtransistor formation region OER. This diode has an n+ diffusion regionNR5, n⁻ epitaxial layer EP, p-type diffusion region PR4, and a p⁺diffusion region PR5.

N⁺ diffusion region NR5 is formed on the main surface of semiconductorsubstrate SUB within n⁻ epitaxial layer EP. P-type diffusion region PR4is formed on the main surface of semiconductor substrate SUB within n⁻epitaxial layer EP. P⁺ diffusion region PR5 is formed on the mainsurface of semiconductor substrate SUB within p-type diffusion regionPR4.

Here, the other configuration in FIG. 21 is almost the same with theconfiguration of the first embodiment shown in FIG. 4 as describedabove, and therefore the same components are denoted with the samecharacters and the detailed description thereof will not be repeated.

Furthermore, although in the foregoing first to third embodiments, oneactive barrier structure is provided between output transistor formationregion OER and control circuit formation region CCR, a plurality ofactive barrier structures may be formed between output transistorformation region OER and control circuit formation region CCR as shownin FIG. 22.

The present invention may advantageously be adopted specifically to asemiconductor device having an active barrier region.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the scopeof the present invention being interpreted by the terms of the appendedclaims.

1-4. (canceled)
 5. A semiconductor device having an output element formation region, an other element formation region, an first active barrier region arranged between said output element formation region and said other element formation region, and a second active barrier region arranged so that said first active barrier region is positioned between said output element formation region and said second active barrier region, comprising: a semiconductor substrate having a main surface; a first region of a first conductivity type formed in said semiconductor substrate in said output element formation region, said other element formation region, said first active barrier region, and said second active barrier region; and an active barrier structure in each of said first and second active barrier regions, said active barrier structure having a second region of the first conductivity type and a third region of the second conductivity type, each of which is in contact with said first region and which are ohmic-connected to each other to attain a floating potential.
 6. The semiconductor device according to claim 5, wherein said second active barrier region surrounded said other element formation region.
 7. The semiconductor device according to claim 5, further comprising an another output element formation region, and a third active barrier region arranged between said output element formation region and said another output element formation region. 